Applied Reconfigurable Computing: 11th International by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C.

By Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz

This publication constitutes the refereed complaints of the eleventh overseas Symposium on utilized Reconfigurable Computing, ARC 2015, held in Bochum, Germany, in April 2015.

The 23 complete papers and 20 brief papers offered during this quantity have been rigorously reviewed and chosen from eighty five submissions. they're equipped in topical headings named: structure and modeling; instruments and compilers; structures and purposes; network-on-a-chip; cryptography purposes; prolonged abstracts of posters. moreover, the publication includes invited papers on funded R&D - operating and accomplished tasks and Horizon 2020 funded projects.

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Extra resources for Applied Reconfigurable Computing: 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings

Example text

Determining Accelerator’s Energy Break-Even Time: Every time an accelerator transitions between the sleep and execution modes, there is an energy penalty. An accelerator should only be power gated if it will be idle long enough to compensate for this penalty. The energy break-even time is the minimum idle time for which an accelerator should be power gated, and can be calculated as: 32 R. Ahmed et al. Tbreak−even = (P1→0 × T1→0 ) + (P0→1 × T0→1 ) PON −leak − POF F −leak (1) where P1→0 , T1→0 , is the power and time required to enter power-saving mode.

Unfortunately, this limits the maximum sparse matrix size that can be processed with the accelerator. To deal with y vectors larger than the OCM size while avoiding DRAM random access latencies, Gregg et al. [4] proposed to store the result vector in highcapacity DRAM and used a small direct-mapped cache. They also observed that cache misses present a significant penalty, and proposed reordering the matrix and processing in cache-sized chunks to reduce miss rate. However, this 18 Y. Umuroglu and M.

If we can distinguish cold misses from the other miss types at runtime, we can avoid them completely: a cold miss to a y element will return the initial value, which is zero1 . Recognizing misses as cold misses is critical for this technique to work. 3. Capacity Misses: Capacity misses occur due to the cache capacity being insufficient to hold the SpMV result vector working set. Therefore, the only way of avoiding capacity misses is ensuring that the vector cache is large enough to hold the working set.

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