Charge-Trapping Non-Volatile Memories: Volume 1 – Basic and by Panagiotis Dimitrakis

By Panagiotis Dimitrakis

This booklet describes the fundamental applied sciences and operation ideas of charge-trapping non-volatile thoughts. The authors clarify the gadget physics of every machine structure and supply a concrete description of the fabrics concerned in addition to the basic homes of the expertise. sleek fabric houses used as charge-trapping layers, for brand spanking new purposes are introduced.

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In the crested tunneling barrier (Baik 2004), a trilayer dielectric stack is formed with a high band-gap (low-k) material sandwiched by a small band-gap dielectric material (high-k) (see Fig. , Si3N4/SiO2/Si3N4. As shown in Fig. 22b, in these dielectric stacks the barrier heights are modulated by the applied gate voltage. 28 P. Dimitrakis Fig. 21 Plot of (a) the energy band-gap vs. dielectric constant and (b) the related energy barriers for electrons and holes with respect to Si (Southwick 2011) As the technology of the tools for the deposition of ultrathin dielectric layers improves, the band-engineering of tunneling dielectric gained a lot of interest in CTM manufacturing.

This is schematically shown in Fig. 15. Also, the coupling capacitance between adjacent cells will be minimized (Fig. 16) because the area of the interacting floating QDs is almost zero compared to the conventional thick-FG layers. Fig. 14 Schematic representation of the QD NVM cell Fig. 15 The role of TOX low resistance defect path in (a) conventional poly-Si FG cell and (b) in QD NVM cell. The inset demonstrates the detail discharging process of a single QD Fig. 16 The coupling capacitance between QDs in adjacent cells is negligible 22 P.

Now, there are commercial devices with embedded Flash memory realized by QDs (Thin Film Storage (TFS) with FlexMemory Technology). In this volume, Chap. 5 is dedicated on quantum-dots nonvolatile memories. 1 Introduction to NVM Devices 25 Fig. 19 The 1-D schematic of the structure (a) and the related equivalent circuit (b) assuming parallel plate capacitor model in the vicinity of a QD. CQC and CQG are the coupling capacitance between the QD-Si and QD-CG respectively. 3 CT Flash Cells Charge-trapping memory (CTM) devices are as old as the FG MOSFET.

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