CMOS High Efficiency On-chip Power Management by John Hu

By John Hu

This ebook offers with the subject material of energy administration built-in circuit (IC) layout, or built-in strength electronics, as a reaction to the starting to be want for energy-efficient electronics. The authors introduce numerous energy administration IC layout innovations to construct destiny energy-efficient “green” electronics. The aim is to accomplish excessive potency, that is necessary to meet shoppers’ growing to be desire for longer battery lives. the focal point is to review topologies amiable for complete on-chip implementation (few exterior elements) within the mainstream CMOS know-how, with a view to decrease the actual dimension and the producing price of the devices.

  • Describes a few concepts at circuits and platforms point that raise sleep-mode potency to delay the battery existence, with out sacrificing functionality parameters;
  • Enables readers to layout for compactness, which calls for fewer cumbersome exterior elements and circuit topologies that lend themselves simply to complete on-chip integration;
  • Offers insights on how the potency boosting concepts for energy administration IC designs paintings towards society’s quest for better strength efficiency.

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Their performance has improved substantially thanks to numerous research on PMOS LDO design techniques. Unless other mentioned, the rest of the chapter will focus on PMOS LDO only. 3 Nevertherless, PMOS LDOs can achieve very good PSR through common-mode ripple cancellation by using of PMOS mirror error amplifier (Gupta et al. 2004). The details are explained in section. 44 3 Linear Regulators VG VDD CLK VBG Charge Pump Vout R1 R2 Design of Besten98JSSC CLK VG CLK VG VDD VBG VDD VBG Vout Vout R1 R1 R2 R2 Design of Kruiskamp08ESSCIRC Design of Giustolisi09AICSP and Camacho09MWSCAS Fig.

In addition to software algorithm, certain SoC level architectural power management strategies can also be applied, such as power domain devision (Hattori et al. 2006), dynamic frequency and voltage scaling (DFVS) (Ma and Bondade 2010), adaptive voltage scaling (AVS) (Carlson and Giolma 2008), and memory retention (Narendra and Chandrakasen 2005; Wang et al. 2008). Power domain division divides a complex SoC cores into different power domains, each enjoying its own supply voltages and leakage current control (often through power gating).

Software power domains DVFS, AVS variable output linear, DC−DC converters SoC Architecture Silicon IPs Fig. 1 A holistic approach to system power management of standby leakage power, and the added transistors and gates increase the dynamic power, making the task of battery extension more challenging (Carlson and Giolma 2008). It was estimated that an average of 10 times better power management scheme is needed from one technology node to another just to maintain the same level of talk and standby time, yet there is an increasing demand for longer battery despite all the technical difficulties (Royannez et al.

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